IP Design Architecture, Specification and Micro-Architecture development Reusable RTL Design for Low Power, Minimum Area and Maximum Speed Synthesis, Timing Clean RTL, CDC, LINT Verilog, VHDL, System Verilog SOC Design RTL Integration, 3rd Party IP Integration ARM, ARC, 8 Bit Processors, Starcore Timing constraints, Low power Clocking, Analog + Dig